SnapEDA's Open Symbol & Footprint Standards Version 1.0

This page outlines the standards we follow at SnapEDA when creating symbols & footprints, and those that we recommend members of our site to follow.

At a high-level, we follow IPC-7351B for footprints (also known as land patterns), and a mix of IEEE-315 for symbols and our own internal standards.

When semiconductor manufacturers provide us with models, we designate the uploader of the model as such. It is more common than not that these models will not follow IPC standards, but rather the manufacturer recommended land patterns.

In addition to looking at who uploaded the model on SnapEDA, it is important to keep in mind that we may have legacy and crowd-sourced content on the site that may not adhere to these standards as rigorously yet. Although we plan to update these models or show where they deviate, the best course of action is to always verify the model before manufacturing.

A big challenge SnapEDA is solving with regards to CAD files is providing transparency into the quality of them, and hence why were released our patent-pending verification checker. This is available on every single part page and will check for common issues. Please review this before downloading, but also be sure to verify the dimensions yourself. Learn more about the checker in this blog post.

Finally, we architected SnapEDA to be able to handle various standards and library preferences dynamically, and therefore it is our intent to be able to support more customizability moving forward. Please let us know if you have particular preferences we should be incorporated.

If you have additional ideas on this front or suggested improvements to our standards, please contact us. We'd especially like to hear from companies and standards organizations who are working on standards that we can be adopting and collaborating on.

1. Symbols

• Name

Use manufacturer's part name (some exceptions to this rule, such as for common symbols such as passives where the generic name is used, like resistors.)


• Pin Configuration


• Inputs on left
• Outputs on right
• VCC & power pins are placed on the upper right for ICs
• GND pins on lower right for ICs
• I/O pins on the middle-left (occasionally middle-right too if there are many)
• Control pins at upper left
• Use one symbol pin per function even if it maps to various package pins*
• Pin type must reflect input type (Ex. io, in, out, pas etc.). for proper ERC/DRC checks


• Special Pins


• No Connect pins are not included on symbol*
• Active-low pins should be designated with a bar above the symbol name
• Clock pins designated with triangle


• Additional Data


• Add MPN above symbol
• Add reference designator and value placeholder below symbol
• Reference designator prefix should be as per

* We understand that preferences here may deviate from our current standards, and have plans to explore customizability

2. Land Patterns (aka "Footprints")

• Name

Use the IPC naming convention


• Land Pattern


• We follow IPC-7351B nominal. In the future, we may provide other densities and standards.

3. Device (Including Symbol-To-Footprint Mappings)

• Device name is Manufacturer’s Part Name (name of the component seen on the website), same name as the Symbol.
• Connect or map the symbol and package and make sure the pins and pads are correctly connected based on the datasheet.
• Add parametric information such as description, manufacturer, value, tolerance (done dynamically upon export from SnapEDA)
• Add the device’s Prefix as per IEEE-315

Please contact us to suggest improvements to these standards.